? semiconductor components industries, llc, 2011 march, 2011 ? rev. 0 1 publication order number: CAV24C64/d CAV24C64 64-kb i 2 c cmos serial eeprom description the CAV24C64 is a 64 ? kb cmos serial eeprom device, internally organized as 8192 words of 8 bits each. it features a 32 ? byte page write buffer and supports the standard (100 khz) and fast (400 khz) i 2 c protocol. external address pins make it possible to address up to eight CAV24C64 devices on the same bus. features ? automotive temperature grade 1 ( ? 40 c to +125 c) ? supports standard and fast i 2 c protocol ? 2.5 v to 5.5 v supply voltage range ? 32 ? byte page write buffer ? hardware write protection for entire memory ? cav prefix for automotive and other applications requiring site and change control ? schmitt triggers and noise suppression filters on i 2 c bus inputs (scl and sda) ? low power cmos technology ? 1,000,000 program/erase cycles ? 100 year data retention ? soic, tssop 8 ? lead packages ? this device is pb ? free, halogen free/bfr free, and rohs compliant figure 1. functional symbol sda scl wp CAV24C64 v cc v ss a 2 , a 1 , a 0 http://onsemi.com pin configuration sda wp v cc v ss a 2 a 1 a 0 1 see detailed ordering and shipping information in the package dimensions section on page 10 of this data sheet. ordering information soic ? 8 w suffix case 751bd scl soic (w), tssop (y) tssop ? 8 y suffix case 948al device address input a 0 , a 1 , a 2 serial data input/output sda serial clock input scl write protect input wp power supply v cc ground v ss function pin name pin function for the location of pin 1, please consult the corresponding package drawing.
CAV24C64 http://onsemi.com 2 device markings (soic ? 8) (tssop ? 8) c64f aymxxx c64f = specific device code a = assembly location y = production year (last digit) m = production month (1-9, o, n, d) xxx = last three digits of assembly lot number = pb ? free package 24c64f = specific device code a = assembly location y = production year (last digit) m = production month (1-9, o, n, d) xxx = last three digits of assembly lot number = pb ? free package 24c64f aymxxx table 1. absolute maximum ratings parameters ratings units storage temperature ?65 to +150 c voltage on any pin with respect to ground (note 1) ?0.5 to +6.5 v stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. 1. during input transitions, voltage undershoot on any pin should not exceed ? 1 v for more than 20 ns. voltage overshoot on pins a 0 , a 1 , a 2 and wp should not exceed v cc + 1 v for more than 20 ns, while voltage on the i 2 c bus pins, scl and sda, should not exceed the absolute maximum ratings, irrespective of v cc . table 2. reliability characteristics (note 2) symbol parameter min units n end (note 3) endurance 1,000,000 program/erase cycles t dr data retention 100 years 2. these parameters are tested initially and after a design or process change that affects the parameter according to appropriat e aec ? q100 and jedec test methods. 3. page mode, v cc = 5 v, 25 c. table 3. d.c. operating characteristics ( v cc = 2.5 v to 5.5 v, t a = ? 40 c to +125 c, unless otherwise speci ed.) symbol parameter test conditions min max units i ccr read current read, f scl = 400 khz 1 ma i ccw write current write, f scl = 400 khz 2 ma i sb standby current all i/o pins at gnd or v cc t a = ? 40 c to +125 c 5 a i l i/o pin leakage pin at gnd or v cc 2 a v il input low voltage ? 0.5 0.3 x v cc v v ih input high voltage a 0 , a 1 , a 2 and wp 0.7 x v cc v cc + 0.5 v scl and sda 0.7 x v cc 5.5 v ol output low voltage v cc > 2.5 v, i ol = 3 ma 0.4 v
CAV24C64 http://onsemi.com 3 table 4. pin impedance characteristics (v cc = 2.5 v to 5.5 v, t a = ? 40 c to +125 c, unless otherwise speci ed.) symbol parameter conditions max units c in (note 4) sda i/o pin capacitance v in = 0 v, t a = 25 c 8 pf c in (note 4) input capacitance (other pins) v in = 0 v, t a = 25 c 6 pf i wp (note 5) wp input current v in < v ih , v cc = 5.5 v 130 a v in < v ih , v cc = 3.3 v 120 v in < v ih , v cc = 2.5 v 80 v in > v ih 2 i a (note 5) address input current (a0, a1, a2) product rev f v in < v ih , v cc = 5.5 v 50 a v in < v ih , v cc = 3.3 v 35 v in < v ih , v cc = 2.5 v 25 v in > v ih 2 4. these parameters are tested initially and after a design or process change that affects the parameter according to appropriat e aec ? q100 and jedec test methods. 5. when not driven, the wp, a0, a1 and a2 pins are pulled down to gnd internally. for improved noise immunity, the internal pull ? down is relatively strong; therefore the external driver must be able to supply the pull ? down current when attempting to driv e the input high. to conserve power, as the input level exceeds the trip point of the cmos input buffer (~ 0.5 x v cc ), the strong pull ? down reverts to a weak current source. table 5. a.c. characteristics (v cc = 2.5 v to 5.5 v, t a = ? 40 c to +125 c, unless otherwise specified.) (note 6) symbol parameter standard fast units min max min max f scl clock frequency 100 400 khz t hd:sta start condition hold time 4 0.6 s t low low period of scl clock 4.7 1.3 s t high high period of scl clock 4 0.6 s t su:sta start condition setup time 4.7 0.6 s t hd:dat data in hold time 0 0 s t su:dat data in setup time 250 100 ns t r sda and scl rise time 1000 300 ns t f (note 6) sda and scl fall time 300 300 ns t su:sto stop condition setup time 4 0.6 s t buf bus free time between stop and start 4.7 1.3 s t aa scl low to data out valid 3.5 0.9 s t dh data out hold time 100 100 ns t i (note 6) noise pulse filtered at scl and sda inputs 100 100 ns t su:wp wp setup time 0 0 s t hd:wp wp hold time 2.5 2.5 s t wr write cycle time 5 5 ms t pu (notes 7, 8) power ? up to ready mode 1 1 ms 6. test conditions according to ?ac test conditions? table. 7. tested initially and after a design or process change that affects this parameter. 8. t pu is the delay between the time v cc is stable and the device is ready to accept commands. table 6. a.c. test conditions input levels 0.2 x v cc to 0.8 x v cc input rise and fall times 50 ns input reference levels 0.3 x v cc , 0.7 x v cc output reference levels 0.5 x v cc output load current source: i ol = 3 ma; c l = 100 pf
CAV24C64 http://onsemi.com 4 power-on reset (por) each CAV24C64 incorporates power-on reset (por) circuitry which protects the internal logic against powering up in the wrong state. the device will power up into standby mode after v cc exceeds the por trigger level and will power down into reset mode when v cc drops below the por trigger level. this bi-directional por behavior protects the device against ?brown-out? failure following a temporary loss of power. pin description scl: the serial clock input pin accepts the clock signal generated by the master. sda: the serial data i/o pin accepts input data and delivers output data. in transmit mode, this pin is open drain. data is acquired on the positive edge, and is delivered on the negative edge of scl. a 0 , a 1 and a 2 : the address inputs set the device address that must be matched by the corresponding slave address bits. the address inputs are hard-wired high or low allowing for up to eight devices to be used (cascaded) on the same bus. when left floating, these pins are pulled low internally. wp: when pulled high, the write protect input pin inhibits all write operations. when left floating, this pin is pulled low internally. functional description the CAV24C64 supports the inter-integrated circuit (i 2 c) bus protocol. the protocol relies on the use of a master device, which provides the clock and directs bus traffic, and slave devices which execute requests. the CAV24C64 operates as a slave device. both master and slave can transmit or receive, but only the master can assign those roles. i 2 c bus protocol the 2-wire i 2 c bus consists of two lines, scl and sda, connected to the v cc supply via pull-up resistors. the master provides the clock to the scl line, and either the master or the slaves drive the sda line. a ?0? is transmitted by pulling a line low and a ?1? by letting it stay high. data transfer may be initiated only when the bus is not busy (see a.c. characteristics). during data transfer, sda must remain stable while scl is high. start/stop condition an sda transition while scl is high creates a start or stop condition (figure 2). the start consists of a high to low sda transition, while scl is high. absent the start, a slave will not respond to the master. the stop completes all commands, and consists of a low to high sda transition, while scl is high. device addressing the master addresses a slave by creating a start condition and then broadcasting an 8-bit slave address. for the CAV24C64, the first four bits of the slave address are set to 1010 (ah); the next three bits, a 2 , a 1 and a 0 , must match the logic state of the similarly named input pins. the r/w bit tells the slave whether the master intends to read (1) or write (0) data (figure 3). acknowledge during the 9 th clock cycle following every byte sent to the bus, the transmitter releases the sda line, allowing the receiver to respond. the receiver then either acknowledges (ack) by pulling sda low, or does not acknowledge (noack) by letting sda stay high (figure 4). bus timing is illustrated in figure 5. start condition stop condition sda scl figure 2. start/stop timing figure 3. slave address bits 1010 device address a 2 a 1 a 0 r/w
CAV24C64 http://onsemi.com 5 figure 4. acknowledge timing 189 start scl from master bus release delay (transmitter) bus release delay (receiver) data output from transmitter data output from receiver ack setup ( t su:dat ) ack delay ( t aa ) figure 5. bus timing scl sda in sda out t buf t su:sto t su:dat t r t aa t dh t low t high t low t su:sta t hd:sta t hd:dat t f write operations byte write to write data to memory, the master creates a start condition on the bus and then broadcasts a slave address with the r/w bit set to ?0?. the master then sends two address bytes and a data byte and concludes the session by creating a stop condition on the bus. the slave responds with ack after every byte sent by the master (figure 6). the stop starts the internal write cycle, and while this operation is in progress (t wr ), the sda output is tri-stated and the slave does not acknowledge the master (figure 7). page write the byte w rite operation can be expanded to page w rite, by sending more than one data byte to the slave before issuing the stop condition (figure 8). up to 32 distinct data bytes can be loaded into the internal page write buffer starting at the address provided by the master. the page address is latched, and as long as the master keeps sending data, the internal byte address is incremented up to the end of page, where it then wraps around (within the page). new data can therefore replace data loaded earlier. following the stop, data loaded during the page write session will be written to memory in a single internal write cycle (t wr ). acknowledge polling as soon (and as long) as internal write is in progress, the slave will not acknowledge the master. this feature enables the master to immediately follow-up with a new read or write request, rather than wait for the maximum specified write time (t wr ) to elapse. upon receiving a noack response from the slave, the master simply repeats the request until the slave responds with ack. hardware write protection with the wp pin held high, the entire memory is protected against write operations. if the wp pin is left floating or is grounded, it has no impact on the write operation. the state of the wp pin is strobed on the last falling edge of scl immediately preceding the 1 st data byte (figure 9). if the wp pin is high during the strobe interval, the slave will not acknowledge the data byte and the write request will be rejected. delivery state the CAV24C64 is shipped erased, i.e., all bytes are ffh.
CAV24C64 http://onsemi.com 6 slave address s a * * * c k a c k a c k s t o p p s t a r t a c k bus activity: master slave address byte address byte data byte figure 6. byte write sequence *a 15 ? a 13 are don?t care bits. a 15 ? a 8 a 7 ? a 0 d 7 ? d 0 figure 7. write cycle timing stop condition start condition address ack 8th bit byte n scl sda t wr slave address s a c k a c k a c k s t a r t a c k s t o p a c k a c k p a c k bus activity: master slave address byte address byte data byte n data byte n+1 data byte n+p figure 8. page write sequence figure 9. wp timing 189 1 8 address byte data byte scl sda wp t su:wp t hd:wp a 7 a 0 d 7 d 0
CAV24C64 http://onsemi.com 7 read operations immediate read to read data from memory, the master creates a start condition on the bus and then broadcasts a slave address with the r/w bit set to ?1?. the slave responds with ack and starts shifting out data residing at the current address. after receiving the data, the master responds with noack and terminates the session by creating a stop condition on the bus (figure 10 ). the slave then returns to standby mode. selective read to read data residing at a speci c address, the selected address must rst be loaded into the internal address register. this is done by starting a byte write sequence, whereby the master creates a start condition, then broadcasts a slave address with the r/w bit set to ?0? and then sends two address bytes to the slave. rather than completing the byte write sequence by sending data, the master then creates a start condition and broadcasts a slave address with the r/w bit set to ?1?. the slave responds with ack after every byte sent by the master and then sends out data residing at the selected address. after receiving the data, the master responds with noack and then terminates the session by creating a stop condition on the bus (figure 11). sequential read if, after receiving data sent by the slave, the master responds with ack, then the slave will continue transmitting until the master responds with noack followed by stop (figure 12). during sequential read the internal byte address is automatically incremented up to the end of memory, where it then wraps around to the beginning of memory. figure 10. immediate read sequence and timing scl sda 8th bit stop no ack data out 89 slave address s a c k data byte n o a c k s t o p p s t a r t bus activity: master slave figure 11. selective read sequence slave address s a c k a c k a c k s t a r t slave s a c k s t a r t p s t o p address byte address byte address n o a c k data byte bus activity: master slave figure 12. sequential read sequence s t o p p slave address a c k a c k a c k n o a c k a c k data byte n data byte n+1 data byte n+2 data byte n+x bus activity: master slave
CAV24C64 http://onsemi.com 8 package dimensions soic 8, 150 mils case 751bd ? 01 issue o e1 e a a1 h l c e b d pin # 1 identification top view side view end view notes: (1) all dimensions are in millimeters. angles in degrees. (2) complies with jedec ms-012. symbol min nom max a a1 b c d e e1 e h 0o 8o 0.10 0.33 0.19 0.25 4.80 5.80 3.80 1.27 bsc 1.75 0.25 0.51 0.25 0.50 5.00 6.20 4.00 l 0.40 1.27 1.35
CAV24C64 http://onsemi.com 9 package dimensions tssop8, 4.4x3 case 948al ? 01 issue o e1 e a2 a1 e b d c a top view side view end view 1 l1 l notes: (1) all dimensions are in millimeters. angles in degrees. (2) complies with jedec mo-153. symbol min nom max a a1 a2 b c d e e1 e l1 0o 8o l 0.05 0.80 0.19 0.09 0.50 2.90 6.30 4.30 0.65 bsc 1.00 ref 1.20 0.15 1.05 0.30 0.20 0.75 3.10 6.50 4.50 0.90 0.60 3.00 6.40 4.40
CAV24C64 http://onsemi.com 10 example of ordering information CAV24C64we ? gt3 (note 11) prefix device # suffix company id cav 24c64 w product number 24c64 e ? gt3 package e = automotive ( ? 40 c to +125 c) temperature range w: soic, jedec y: tssop t: tape & reel 3: 3,000 / reel lead finish g: nipdau tape & reel (note 13) 9. all packages are rohs-compliant (lead-free, halogen-free). 10. the standard lead finish is nipdau. 11. the device used in the above example is a CAV24C64we ? gt3 (soic, automotive temperature, nipdau, tape & reel, 3,000/reel). 12. for other package options, please contact your nearest on semiconductor sales office. 13. for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and ree l packaging specifications brochure, brd8011/d. on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. CAV24C64/d on semiconductor is licensed by philips corporation to carry the i 2 c bus protocol. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5773 ? 3850 literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative
|
